hb2_ee4c – A performance optimized encryption engine.
The 4-clock implementation of Hummingbird is targeted at fast encryption (4 clocks) and maximum throughput and bandwidth. The 4 clock Soft IP package delivers “out-of- the-box” implementation under 26k um2 of area (3220 GE) and 163uW of peak power, in a 0.13um technology, while delivering 40Mb/s of encryption at an operating frequency of 10Mhz.

hb2_ee20c – A size optimized encryption engine.
The 20-clock implementation of Hummingbird is targeted at ultra low area and power. The 20 clock Soft IP package delivers “out-of-the-box” implementation under 18k um2 of area (2159 GE) and 149uW of peak power, in a 0.13um technology, while delivering 40Mb/s of encryption at an operating frequency of 10Mhz.

The following hardware IP packages are available for RFID reader integration:

hb2_ce4c – An encrypt/decrypt engine optimized for performance.
The engine performs encryption, decryption, random number generation and hash-number generation. It includes two random-number generation modes to ignore the data input and use its own state to generate pseudo-random word values. Configurable for “bus access” or “serial access” for quick save and restore while servicing multiple read requests. Two reference designs illustrate the use of the block in each model.

hb2_fk5s – fast key search engine.
The fast key search engine allows quick and secure key searches through the key database. The block employs five “slices” of the HB-2 encrypt engine optimized for this use. Due to the parallel engines and Hummingbird's small block size the fast key engine can search through a database of 16 million keys in 92ms (at a clock rate of 300kHz).

All of the HW IP packages are built for easy integration into a standard EDA flow and come with the following:
RTL code - In VHDL and Verilog form. Written using standard practices to ensure compilation and synthesis with any toolset.

Reference Design -  The reference design provides a detail example of the use of the block. In many cases the reference design RTL can be used as the starting point for the integration of the IP

Full Documentation – Detailed documentation for the block and the reference design.

Simulation scripts – The simulation script performs simulation verification of the reference design. All simulation scripts are written for the modelism simulation tool but due to the intentional simplicity can be easily ported to any simulator.

Synthesis scripts – The syntheses are written for the Cadence RTL Compiler but like the simulation scripts can be easily ported to other synthesis tools.